The present invention relates to a multi-processor system having a shared memory unit and more particularly to a multi-processor type storage control apparatus.
In recent storage systems, a system of the type having multi-processor architecture has been employed principally with the aim of obtaining higher performance.
For example, in a prior art shown in xe2x80x9cHITAC H8538-C3 type disc control apparatusxe2x80x9d, p5, 1985, the apparatus has storage directors each of which controls data transfer between a central processing unit (CPU) and a storage unit, and a cache memory that temporally stores data of the storage units. The two or more storage directors are connected to the cache memory and each of the storage directors has an access path to the cache memory. Such an arrangement is called xe2x80x9cstar connectionxe2x80x9d. There are processors running micro programs that control data transmission and related hardware in the storage director. The apparatus also has a shared memory which stores information, such as cache and disc management data, with-which the processors work consistently. The storage directors and the shared memory are connected in a similar manner to the cache memory through different access paths.
On the other hand, in another prior art shown in xe2x80x9cHITAC A6591 type disc control apparatusxe2x80x9d, p4, 1997, the control apparatus has a plurality of processors on the host side, a plurality of processors on the storage unit side, a cache memory unit and a shared memory unit. Each of the processors is coupled to the shared memory unit through a control bus and each of the processors is coupled to the cache memory unit through a data bus.
In the above prior arts, the shared memory unit has a dual structure of shared memory sections with the aim of securing the reliability, so that even when one of the shared memory sections is blocked, normal operation of the system can be ensured. In the conventional system, for the purpose of maintaining the dual state of the shared memory unit, a method is employed in which when write access to the shared memory unit occurs, circuits of both the shared memory sections receive the access and at the same time, update a designated address.
On the other hand, in the former prior art, such control as above is not carried out and when there occurs updating, addresses on both the shared memory sections are updated sequentially in accordance with a program operated by the processor.
To meet a need for high performance required for the storage apparatus system, the control unit is increased in scale and components are increased in speed so that for example, the number of processors may be increased, the capacity of the cache memory unit may be increased, high-performance processors may be employed, the width of internal buses may be expanded and the bus transfer capability may be improved.
In the latter prior art disclosed in xe2x80x9cHITAC A6591 type disc control apparatusxe2x80x9d, however, the transfer capability of the internal paths has been liable to encounter difficulties in following an increase in scale of the system and improvements in performance.
Especially, the control path has a small transfer amount per transfer operation, with the result that most of occupation time is used for protocol overhead and the transfer capability of the path cannot fulfil itself.
Accordingly, in order to obtain high memory access performance, it is conceivable to couple the processor and the memory unit in a star connecting fashion as in the former prior art system disclosed in the xe2x80x9cHITAC H-8538-C3 type disc control apparatusxe2x80x9d.
However, the number of access paths for coupling the shared memory unit and the cache memory unit increases in proportion to an increase in the number of carried processors.
The number of pins in an existing LSI amounts up to a maximum of about 600.
On the other hand, on assumption that the width of access paths inclusive of control line is about 20 bits and the number of processors is 64, input lines of 1280 bits in total are laid to each of the shared memory unit and the cache memory unit, giving rise to a shortage of the number of pins in the LSI.
Further, since the size of a package is limited, there is an upper limit of the number of connectors on the package, making it impossible to lay the input lines of 1280 bits.
Accordingly, a first object of the present invention is to provide a storage control apparatus having an internal construction which can avoid a shortage of the number of pins and that of the number of connectors in an LSI and can secure necessarily sufficient performance.
On the other hand, in the shared memory unit having a dual structure, the sequence of access to dual sections by the individual processors must be maintained.
This problem will be described by way of example.
Incidentally, as will be well known in the art, access to the cache memory unit is carried out by using management information in the shared memory unit. More particularly, management information for each segment of the cache memory unit (information indicative of use/nonuse of each segment and information indicative of locking/unlocking of each segment) is stored in the shared memory unit. When the processor accesses the cache memory unit, it decides from the management information in the shared memory unit whether or not a segment to be accessed is in use. In case the segment is in nonuse, the processor accesses that segment of the cache memory unit. Through this, a plurality of processors are prevented from writing/reading to/from the cache memory unit simultaneously.
Thus, it is now assumed that for example, processors a and b update the contents of the shared memory unit substantially simultaneously.
If the contents of a section A of the shared memory unit is first updated by the processor a and the contents of a section B of the shared memory unit is updated by the processor b, followed by subsequent updating of the contents of the section A by the processor b and subsequent updating of the contents of the section B by the processor a, the shared memory unit has the ultimate contents including the contents of section A which is updated by the processor b and the contents of section B which is updated by the processor a, thus indicating that states of both the sections do not coincide with each other.
In the aforementioned xe2x80x9cHITAC H-6581-C3 disc type control apparatusxe2x80x9d, a method is proposed as a means for securing the access sequence, according to which the individual processors are exclusively ORed programmably and thereafter, the same addresses in both the shared memory sections are updated sequentially.
In the above method, however, the memory unit is once locked and then updated, raising a problem from the standpoint of performance.
Accordingly, a second object of the present invention is to maintain the dual state of the two shared memory sections.
According to an aspect of the present invention, a storage control apparatus coupled to a central processing unit and a storage unit to control input/output of data between the central processing unit and the storage unit, comprises at least two processors coupled to the central processing unit and the storage unit, a cache memory unit for temporarily storing data of the storage unit, a shared memory unit for storing information concerning control of the cache memory unit and the storage unit, and a selector coupled to each of the at least two processors, the cache memory unit and the shared memory unit through access paths to selectively apply access requests from the at least two processors to the cache memory unit and the shared memory unit.
With this construction, the total number of access paths for coupling the selector and the shared memory unit or the total number of access paths for coupling the selector and the cache memory unit can be smaller than the total number of access paths for coupling the at least two processors and the selector, thereby reducing the number of paths (pins) laid to each memory unit. A similar effect can also be attained when a single memory unit is used to serve as both a cache memory unit and a shared memory unit.
According to an embodiment of the present invention, the shared memory unit includes paired two shared memory sections each coupled to the selector, the two shared memory sections are coupled to each other by an inter-shared memory path, the selector applies an access request from one of the at least two processors to one of the two shared memory sections, the one shared memory section responds to the applied access request to perform an access process and sends a command to the other of the two shared memory sections, and the other shared memory section responds to the command to perform an access process. With this construction, by making a read/write access request to one of the two shared memory sections through the selector, the read/write processes for the two shared memory sections can be carried out simultaneously.
According to another embodiment of the present invention, the cache memory unit has a dual structure of first and second cache memory sections, the processors send access requests to the selector, and the selector responds to the access requests to access the two cache memory sections. With this construction, in accordance with the access requests made by the processors through one operation, the two cache memory sections can be accessed.
According to still another embodiment, the cache memory unit has a dual structure of first and second cache memory sections, the processors send to the selector commands for designating data copying between the first and second cache memory sections, and the selector responds to the commands to perform the data copying between the first and second cache memory sections. With this construction, the data copying between the two cache memory sections can be effected by one commanding operation from the processors.